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[VHDL-FPGA-Verilog] ade

Description: 用VERILOG HDL 语言实现一个8位串行乘法器-VERILOG HDL language with an 8-bit serial multiplier
Platform: | Size: 1024 | Author: xiaobai | Hits:

[VHDL-FPGA-Verilog] spi_latest.tar

Description: spi接口 verilog版本, Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations:-spi interface, verilog version, Synchronous serial interfaces are widely used to provide economical board-level interfaces between different devices such as microcontrollers, DACs, ADCs and other. Although there is no single standard for a synchronous serial bus, there are industry-wide accepted guidelines based on two most popular implementations:
Platform: | Size: 2624512 | Author: shen | Hits:

[VHDL-FPGA-Verilog] sim_uart

Description: uart 收发器 verilog 代码，实现自收发功能 sys clk = 25m, baud 9600 停止位1， 无校验位； 代码实现了串口自收发功能，及把从 PC 收到的内容都发送会 PC, 其他波特率，自行修改代码即可，在 alter 的FPGA 上调试通过； -verilog code uart transceiver to achieve self-transceiver function sys clk = 25m, baud 9600 1 stop bit, no parity code from the transceiver features a serial port, and the contents received from the PC will send the PC, another Potter rate, self-modifying code can, in the alter of the FPGA, debugging through
Platform: | Size: 2048 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] sdram

Description: 通过 UART 读写 SDRAM verilog 源代码 通过 UART 的接口发送命令来读写 SDRAM 命令格式如下： 00 02 0011 1111 2222 00： 写数据 02： 写个数 0011： 写地址 1111 2222： 写数据， 是 16 bit， 每写完一个数据，向串口发送 FF 回应； 输出： FF FF 01 03 0044 01: 读sdram 03： 读的个数 0044: 读的地址 输出： xxxx xxxx xxxx sdram 在 0044 0045 0046 处的数据； sdram 使用的是 K4S161622D.pdf 系统时钟 25m， 通过 PLL 得到 SDRAM clk 100m sdram controller clk 100m， 前者相对后者2ns 相移 -Read and write through the UART SDRAM verilog source code through the UART interface to send commands to SDRAM read and write command format is as follows: 0,002,001,111,112,222 00: Write Data 02: Write the number of 0011: write address 11112222: write data, is 16 bit, each completed a data, respond to the serial port FF output: FF FF 01 03 0044 01: Reading sdram 03: 0044 the number of read: Read the address output: xxxx xxxx xxxx sdram at 004,400,450,046 at the data sdram use system clock is K4S161622D.pdf 25m, obtained by PLL SDRAM clk 100m sdram controller clk 100m, the former phase shift relative to the latter 2ns
Platform: | Size: 14336 | Author: 周西东 | Hits:

[VHDL-FPGA-Verilog] serial

Description: 基于FPGA的串口程序，Verilog语言编写，程序完整-FPGA-based serial procedures, Verilog language, the program integrity
Platform: | Size: 994304 | Author: toutoublue | Hits:

[VHDL-FPGA-Verilog] FPGA_Interface_verilog

Description: verilog数字接口实验程序，包括USB，矩阵键盘，蜂鸣器，串口，i2c总线接口程序实例。-verilog digital interface for experimental procedures, including the matrix keyboard, buzzer, serial, i2c bus interface program instance.
Platform: | Size: 2796544 | Author: wylie | Hits:

[VHDL-FPGA-Verilog] IS61WV51216BLL

Description: 备注：使用的是VeriLog HDL语言 软件环境xilinx ISE 10.1，硬件：高教仪EXCD-1FPGA电路板。FPGA信号：spartan-3e . 功能编写硬件描述性语言实现FPGA对板上外设SRAM IS61WV51216BLL的读写，通过串口发送到上位机上，使用串口助手显示读取的数据。-Note: Use the VeriLog HDL language software environment xilinx ISE 10.1, hardware: Higher Miriam EXCD-1FPGA circuit boards. FPGA Signal: spartan-3e. Write functional hardware description language implementation of on-board peripherals SRAM IS61WV51216BLL FPGA to read and write, sent to the host computer through the serial port, use the serial Assistant displays the data read.
Platform: | Size: 5120 | Author: 李钿 | Hits:

[VHDL-FPGA-Verilog] SDH

Description: SDH开销的接收处理，要求： 1， A1和A2字节为帧头指示字节，A1为“11110110”，A2为“00101000”，连续3个A1字节后跟连续3个A2字节表示SDH一帧的开始。要求自行设计状态机，从连续传输的SDH字节流中找出帧头。 2， E2字节为勤务话通道开销，用于公务联络语音通道，其比特串行速率为64KHz(8*8K=64)。要求从SDH字节流中，提取E2字节，并按照64K速率分别串行输出E2码流及时钟，其中64K时钟要求基本均匀。（输出端口包括串行数据和64K串行时钟） -Receiving SDH overhead processing requirements: 1, A1 and A2 bytes instruction byte header, A1 is " 11110110" , A2 is " 00101000" , for three consecutive A1 bytes followed by three A2 bytes of an SDH the beginning of the frame. Asked to design a state machine, from the continuous stream of bytes in the SDH transmission header to find out. 2, E2-byte path overhead for the service, then, for the public to contact voice channels, the bit-serial rate 64KHz (8* 8K = 64). SDH byte stream request from the extraction E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock requires 64K basic uniform. (Including the serial data output port and 64K serial clock)
Platform: | Size: 2048 | Author: 刘镇宇 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 语言：verilog语言 功能：通过串口控制模块，实现FPGA与串口 通信。 仿真环境：modelsim 综合环境：quartus -Language: verilog language function: through the serial port control module, FPGA and serial communication. Simulation Environment: modelsim integrated environment: quartus II
Platform: | Size: 64512 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] I2C

Description: 语言：verilog 功能：用Verilog HDL编写的I2C主机串行通信的程序。两条总线线路：一条串行数据线 SDA， 一条串行时钟线 SCL；串行的 8 位双向数据传输位速率在标准模式下可达 100kbit/s，快速模式下可达 400kbit/s ，高速模式下可达 3.4Mbit/s；在数据传输过程中，当时钟线为高电平时，数据线必须保持稳定。如果时钟线为高电平时数据线电平发生变化，会被认为是控制信号。 仿真工具：modelsim 综合工具：quartus -Language: verilog Function: I2C written in Verilog HDL with the host serial communication program. Two bus lines: a serial data line SDA, a serial clock line SCL 8-bit bi-directional serial data transmission bit rate in the standard mode of up to 100kbit/s, fast mode, up to 400kbit/s, high-speed mode of up to 3.4Mbit/s in the data transmission process, when the clock line is high, the data line must remain stable. If the clock line is high level when the data line changes will be considered is the control signal. Simulation tools: modelsim synthesis tool: quartus II
Platform: | Size: 8192 | Author: huangjiaju | Hits:

[VHDL-FPGA-Verilog] uartTransceiver

Description: Verilog Serial port
Platform: | Size: 1024 | Author: Kemper | Hits:

[VHDL-FPGA-Verilog] Flash_Ctrl

Description: 串行flash的写及擦除操作，串行flash，spi接口，支持并口输出-Serial flash write and erase operations, serial flash, spi interface, support for parallel port output
Platform: | Size: 1024 | Author: 王伯祥 | Hits:

[VHDL-FPGA-Verilog] 12.4Uart

Description: 最简单的verilog串口发送接收源代码,已经上机调试,请放心,直接使用-Simple transmit and receive serial verilog source code, has been on the machine commissioning, please rest assured, direct use
Platform: | Size: 203776 | Author: 大方的 | Hits:

[VHDL-FPGA-Verilog] dct01

Description: Verilog编写的串口通讯下解码状态机-Verilog serial communication prepared under the decoder state machine
Platform: | Size: 293888 | Author: tagpair | Hits:

[VHDL-FPGA-Verilog] ad5399

Description: AD5399是一款串行输入、双通道、12位数模转换器，可采用二进制补码数字编码。。 用Verilog实现其配置与功能-AD5399 is a serial input, dual-channel, 12-bit DAC, digital code can be twos complement. . Configuration and use Verilog functions to achieve its
Platform: | Size: 1024 | Author: dengxiaosong | Hits:

[VHDL-FPGA-Verilog] serial_adder

Description: This is a simple Serial Adder for Quartus II. The source code is in verilog HDL
Platform: | Size: 392192 | Author: Junkie | Hits:

[VHDL-FPGA-Verilog] DA

Description: Verilog HDL　写的１２位串口ＤＡ转换程序-Written in Verilog HDL conversion process 12-bit serial DA
Platform: | Size: 684032 | Author: xiong | Hits:

[VHDL-FPGA-Verilog] URAT

Description: Verilog硬件描述语言，RS232串口发送接收程序-Verilog hardware description language, RS232 serial port send and receive program
Platform: | Size: 1024 | Author: zhaoyf | Hits:

[VHDL-FPGA-Verilog] new-piso

Description: its hdl code and test bench for paralell in serial out design...written in verilog and by haneesh
Platform: | Size: 2048 | Author: haneesh | Hits:

[VHDL-FPGA-Verilog] serial

Description: 程序实现fpga与pc机的通讯，verilog语言-Program realization fpga with the PC communications, verilog language
Platform: | Size: 3072 | Author: 白羽 | Hits:
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